Allystar Technology Co. Limited Hiring! Full Time IC Layout Engineer in Hong Kong - Ricebowl

Job Responsibilities：
Layout Design and Implementation: Responsible for chip floorplanning (including at the TOP level and module level), physical implementation (placement and routing), and comprehensive verification (such as DRC, LVS, DFM) to ensure the design complies with process rules and performance targets.
Verification and Optimization: Conduct physical verification, parasitic parameter extraction and post-simulation using EDA tools (e. g. Calibre), optimize the performance of the layout, and compile relevant design documents.
Process and Collaboration: Establish and optimize layout design processes and specifications; serve as the project lead layout engineer (TOP Layout), take charge of or be deeply involved in layout planning, and collaborate closely with teams including circuit design, process, and testing to ensure successful tapeout.
Data Delivery and Verification: Responsible for or involved in generating the final tapeout data package (GDSII) and completing pre-tapeout data verification (JDV)

Qualifications：
Academic Background: Bachelor's degree or above, majoring in microelectronics, electronic engineering, materials, physics or other related fields.
Professional Skills:
Proficient in mainstream layout design tools such as Cadence Virtuoso and Synopsys IC Compiler, as well as physical verification tools including Calibre.
Familiarity with semiconductor processes and procedures such as CMOS, BCD, and FinFET, with successful tapeout experience is preferred.
Deeply understand the key knowledge of layout design, such as parasitic effects, device matching, signal integrity, ESD, Latch-up and other reliability design contents.
Additional Capabilities:
Good at XFN communication and coordination, and a strong team player.
Those who master scripting languages such as Skill, Python and Perl, and are capable of automation design or Pcell development are preferred.
Candidates with experience in complex chip layout design such as digital-analog hybrid, high-voltage or radiofrequency chips are preferred.