Physical Design Engineer
Job Summary
We are looking for a Physical Design Engineer with hands-on experience in ASIC physical design from Netlist to GDSII. The ideal candidate should have experience in physical implementation, timing closure, and physical verification for advanced technology nodes.
Job Type: Full Time - Onsite (Permanent and Contract)
Job Location: Penang, Malaysia
Job Mode: Onsite
Salary: Depends on your Skills and Experience
Position Open For: Person Legally authorized to work in Malaysia (No Visa Sponsorship)
Key Responsibilities
- Perform ASIC physical design from Netlist to GDSII.
- Handle floor planning, placement, clock tree synthesis (CTS), and routing.
- Perform timing closure and resolve setup/hold timing violations.
- Conduct static timing analysis (STA) and optimize design performance.
- Perform physical verification including DRC, LVS, ERC, and antenna checks.
- Analyze and optimize power delivery, IR-drop, and signal integrity.
- Develop and maintain automation scripts using Tcl, Perl, or Python.
- Work closely with front-end design, DFT, and verification teams to achieve project milestones.
Requirements
- Bachelor's or master's degree in electrical, Electronic, Computer Engineering, or a related field.
- Minimum 4 years of experience in ASIC Physical Design.
- Strong understanding of the ASIC implementation flow from Netlist to GDSII.
- Hands-on experience with Synopsys IC Compiler II (ICC2), Primetime or Cadence Innovus, Tempus.
- Good knowledge of Static Timing Analysis (STA), CTS, placement, routing, and timing closure.
- Experience with advanced technology nodes such as 7nm, 5nm, or 3nm is preferred.
- Proficiency in Tcl, Perl, or Python scripting.
- Good analytical, troubleshooting, and communication skills.