UST Hiring! Full Time Design Verification (PLL) Engineer in Pulau Pinang - Ricebowl

Key Responsibilities

• Develop and execute comprehensive verification plans for Clock Generation, PLL, and Clock Management IPs.
• Design and maintain robust SystemVerilog/UVM verification environments and reusable testbenches.
• Verify functional correctness of PLLs, clock controllers, clock muxes, dividers, and clock distribution logic.
• Develop constrained-random and directed test cases to validate clock switching, frequency scaling, reset sequencing, power management, and related scenarios.
• Perform functional coverage analysis, assertion-based verification (SVA), and regression closure.
• Debug simulation failures and collaborate closely with RTL, analog, and mixed-signal design teams to resolve design issues.
• Participate in verification planning, design reviews, and sign-off activities.
• Drive verification quality improvements through automation and reusable methodologies.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• Minimum 6 years of hands-on experience in Design Verification.
• Strong experience verifying Clock (CLK), PLL, and Clock Management IPs.
• Excellent knowledge of SystemVerilog, UVM, and SVA.
• Strong understanding of digital design, timing concepts, reset architecture, clock domains, and CDC fundamentals.
• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Strong debugging and problem-solving skills.
• Experience with scripting languages such as Python, Perl, or Shell is an advantage.

Preferred Qualifications

• Experience in SoC/IP verification for advanced semiconductor designs.
• Exposure to low-power verification (UPF/CPF) and power-aware simulation.
• Familiarity with mixed-signal verification environments.
• Experience with formal verification and emulation is a plus.