Full Time Senior Design Verification Engineer Jobs, in UST - Ricebowl

Job Responsibilities:

• Develop and execute verification plans for Clock (CLK) and PLL IPs.
• Build and maintain SystemVerilog/UVM-based verification environments and testbenches.
• Create directed and constrained-random test cases to validate functionality and performance.
• Perform functional coverage analysis, debug simulation failures, and root cause issues.
• Collaborate with design, architecture, and validation teams to ensure verification completeness.
• Support regression testing and verification sign-off.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.
• At least 6 years of relevant experience
• Strong knowledge of Clocking (CLK), PLL, clock generation/distribution, and timing concepts.
• Hands-on experience with SystemVerilog, UVM, and Verilog.