Full Time IP Design Engineer (RTL - Synthesis) Jobs, in Silicon One Bayan Lepas - Ricebowl

IP Design Engineer (RTL & Synthesis)

Location: Bayan Lepas, Penang, Malaysia

Job Type: Full-time (On-site)

Silicon One is seeking a high-caliber IP Design Engineer to join our team. In this role, you will be involved in the full development lifecycle—from architecture definition to RTL implementation—shaping world-class FPGA IP solutions for our next-generation networking products.

Key Responsibilities

Architecture & Protocol Research: Deeply understand company FPGA device architectures, application scenarios, classic algorithms, and protocol specifications.

End-to-End IP Development: Analyze market requirements to define architectures and design algorithm models (C/C++, Matlab, etc.). Write RTL code (Verilog/VHDL), create reference designs, and develop verification environments (SystemVerilog).

IP Packaging & Delivery: Utilize EDA tools and scripts to package IPs, including the development of IP GUIs and comprehensive IP package testing.

Technical Support & Training: Provide training to FAEs on IP principles and usage; support FAEs during customer application integration and debugging.

Continuous Improvement: Gather market feedback to drive updates and upgrades for assigned IP portfolios.

Position Requirements

Education: Bachelor’s degree or above in Electronic Engineering, Microelectronics, Communications, or Computer Science.

Experience: Minimum 5+ years of related work experience.

Technical Expertise:

Expertise in Verilog/VHDL and proficiency with Vivado/ISE/Quartus for development and debugging. Digital front-end experience is highly preferred.

Proficient with RTL simulation tools: Synopsys VCS, Verdi, Cadence NC-Verilog, or Mentor ModelSim.

Mastery of Top-Bottom FPGA design methodology, DFT (Design for Test) concepts, and expertise in Timing Closure.

Soft Skills: Proactive research mindset, innovative thinking, strong communication skills, and established project management abilities.

Preferred Qualifications (Added Advantage)

DSP Expertise: Familiarity with Xilinx System Generator and experience in designing or leading a team to design algorithms like FIR, FFT, DUC, DDC, or CFR.

High-Speed Interfaces: Independent or leadership experience in designing protocols such as PCI Express, NVMe, SATA, SRIO, or AURORA.

Why Silicon One?

Full Lifecycle Exposure: Drive designs from initial specification through to successful tape-out.

Competitive Rewards: We offer a highly attractive compensation package for top-tier lead talent.

Apply Now

Ready to lead the future of FPGA IP design?

Send your resume to *************, only shortlisted candidates will be contacted.