Symatics Technology Pte. Ltd. Hiring! Full Time AI Chip Architecture - Compiler Co-Design Engineer in - Ricebowl

3-5 Years Experience

Role Overview:

As a core contributor, you will independently lead the hardware-software co-design of new hardware micro-architectures, design critical compiler passes, and use simulation telemetry to drive early-stage hardware specification decisions.

Responsibilities

• Full-Stack Architecture Exploration: Lead the micro-architecture exploration for next-generation AI accelerators (or LLM/AI accelerators). Build high-precision, highly configurable cycle-accurate performance simulators in C++.
• Core Compiler Pass Development: Own the development of core middle/backend compiler passes (based on MLIR or TVM), including space-time partitioning (Loop Tiling), Layout Optimization, and hardware pipeline scheduling/vectorization algorithms.
• Hardware-Software Co-Optimization: Map cutting-edge AI models (e.g., LLMs, MoE) to proprietary hardware via the compiler infrastructure. Drive end-to-end optimizations and guide the hardware team on sizing SRAM, setting bandwidth metrics, and designing ISAs.
• Technical Problem Solving & Mentorship: Troubleshoot severe performance bottlenecks related to massive-scale distributed computing (3D parallelism) or on-chip memory accesses. Mentor junior engineers and interns.

Qualifications

• Experience & Education: Master’s or Ph.D. degree in Computer Architecture, Microelectronics, or Computer Science, with 3-5 years of industrial experience in AI chip architecture design, GPGPU development, or core AI compiler engineering.
• Advanced Programming: Expert-level knowledge of Modern C++ (C++17/20) with exceptional software architecture design skills. Strong proficiency in multi-threading, high-performance computing (HPC) optimization, and Python (including deep knowledge of PyTorch/TensorFlow internals).
• Technical Depth (True Co-Design Capability):
• Architecture Domain: Deep understanding of NPU/TPU, systolic arrays, or SIMT/SIMD architectures. Expert knowledge of Memory Hierarchy Management, with hands-on experience in on-chip SRAM layout, HBM interfaces, and DMA double-buffering (Ping-Pong data movement).
• Compiler Domain: Highly proficient in MLIR (proven experience with custom Dialects, ODS, and Pattern Rewrite) or TVM (proven experience with TE/TIR, AutoTVM/Ansor). Capable of writing low-level code-generation logic for heterogeneous hardware targets.
• Preferred / Plus:
• Proven track record of a full tape-out cycle where you successfully brought up and ran the compiler toolchain on live silicon.
• Active code contributor or Maintainer in open-source communities like LLVM, MLIR, TVM, or Triton (with substantial PRs merged).
• Publications in top-tier computer architecture or compiler conferences (e.g., ISCA, MICRO, ASPLOS, HPCA, PLDI).

Work Location: In person