Devloit Hiring! Full Time Physical Design Engineer in Pulau Pinang - Ricebowl

Responsibilities:

• Understand design data flow and complexity, translating to physical design constraints and strategy for convergence with best PPA metrices.
• Strategize floor-planning options and experimentation, fine tune Place & Route for design specific needs and close timing requirement within given power envelope.
• Implement Low Power physical design flows and methodologies such as Power-Gating, Clock-Gating and MBR flows.
• Perform and debug LEC in ensuring design equivalence against synthesized gate-level netlist.
• Guiding/leading junior members of the team with effective coaching approach.
• Enhance tools, flows and methodologies to meet design TAT

Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule

Qualifications:

This position requires at least BSEE with 6-10 years of ASIC development experience in a fast paced environment. You are required to have expertise in a wide range of areas in design, tools and flows:

• BEng/MEng in EE or equivalent with the completion of several complexes ASIC or IC tapeouts in VDSM process technology nodes.
• Experience taking large blocks to timing, physical design and DRC/LVS closure.
• Experience in physical design with the understanding of VDSM effects and issues with excellent debugging and analytical skills.
• Understand floor planning, placement and optimization for timing closure, clock network planning, power distribution planning and routing.