UST Malaysia Hiring! Full Time Analog Mixed-Signal Layout Engineer in Pulau Pinang - Ricebowl

We are looking for experienced Analog Mixed-Signal Layout Engineers to join our semiconductor design team. In this role, you will be responsible for the physical implementation of high-performance analog and mixed-signal IPs using advanced process technologies. You will work closely with circuit designers to deliver high-quality, manufacturable layouts that meet stringent performance, reliability, and timing requirements.

Key Responsibilities

• Perform full-custom layout design for analog and mixed-signal circuits using Cadence layout tools.
• Develop layouts for high-speed I/O circuits, including SerDes, DDR I/O, and other high-speed interfaces.
• Implement layouts for analog IPs such as PLLs, DLLs, LDOs, Bandgap References, and other precision analog circuits.
• Create and optimize I/O floorplans and power delivery planning to achieve performance, area, and reliability targets.
• Design and verify I/O ESD protection layouts and perform ESD-related layout analysis.
• Support advanced packaging implementation, including C4 bump planning and Redistribution Layer (RDL) layout.
• Ensure layouts comply with advanced process node design rules, reliability, matching, symmetry, and parasitic requirements.
• Perform layout verification, including DRC, LVS, ERC, and parasitic extraction (PEX), and collaborate with circuit designers to resolve layout-related issues.
• Work closely with design, verification, packaging, and process engineering teams throughout the development cycle.

Required Qualifications

• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field.
• Experience in full-custom analog and mixed-signal IC layout.
• Strong knowledge and hands-on experience in one or more of the following:
• SerDes I/O, DDR I/O, or other high-speed I/O layouts
• PLL and DLL layout implementation
• LDO, Bandgap, and analog power management circuits
• Pure analog circuit layout
• I/O floorplanning and power delivery planning
• I/O ESD layout and analysis
• C4 bump and Redistribution Layer (RDL) implementation
• Proficiency with Cadence layout tools (Virtuoso Layout XL or equivalent).
• Solid understanding of DRC, LVS, ERC, parasitic extraction (PEX), electromigration (EM), IR drop, and reliability considerations.
• Strong knowledge of analog layout techniques, including device matching, common-centroid layout, shielding, guard rings, symmetry, and noise isolation.

Preferred Qualifications

• Experience with advanced semiconductor process technologies of 7nm or below.
• Hands-on layout experience in Samsung 5nm or below process technologies is a strong advantage.
• Familiarity with advanced packaging technologies and high-speed interface layout optimization.
• Experience collaborating with analog circuit designers from floorplanning through silicon validation.

Experience Levels (Hiring Plan)

• 2–4 years: 5 openings
• 4–6 years: 5 openings
• 6–8 years: 5 openings
• 8+ years: 5 openings