全职 Physical Design Engineer 工作, 薪水, Lancesoft Malaysia Pulau Pinang 公司招聘中 - Ricebowl

We're Hiring: Senior Engineer – Synthesis & Static Timing Analysis (STA)

Are you passionate about ASIC implementation and digital design? We are looking for an experienced Senior Engineer to join a leading semiconductor team and contribute to cutting-edge chip development.

Location: Bayan Lepas, Malaysia

Experience: 5+ Years

Qualification: Bachelor's or Master's Degree in Engineering

Key Responsibilities

Perform Synthesis, Logic Equivalence Checking (LEC), Low Power Checks, Memory BIST Insertion, and Constraint Validation.

Execute full-chip, subsystem, and block-level Static Timing Analysis (STA).

Run RTL Lint, CLP, BIST, and DFT insertion flows.

Collaborate with RTL Design, Physical Design, and DFT teams to ensure high-quality netlist delivery.

Develop TCL scripts and analyze/debug implementation flows.

Handle ECO implementation and Logic Equivalence Checking (LEC).

Mentor junior engineers and drive best practices across implementation flows.

Required Skills

Strong experience with ASIC Synthesis methodologies.

Hands-on expertise with DC, Genus, Fusion Compiler, PrimeTime, Tempus, Formality, and Conformal.

Strong knowledge of timing constraints for Synthesis, STA, and Physical Design.

Experience with scripting using TCL, Perl, or Python.

Ability to work independently with Design, DFT, and Physical Design teams.

Preferred Skills

Knowledge of DFT methodologies.

Experience with UPF (Unified Power Format) and power estimation.

Familiarity with additional EDA tools.

Exposure to AI-assisted engineering, including:

If you're looking to work on advanced semiconductor technologies in a collaborative and innovative environment, we'd love to hear from you!