XINPAL Hiring! Full Time Physical Design Engineer in Pulau Pinang - Ricebowl

We are seeking a Physical Design Engineer to drive end-to-end semiconductor backend implementation, including synthesis, floorplanning, placement, CTS, routing, STA, timing closure, and physical verification. The role focuses on advanced technology node designs (16nm–3nm), optimizing performance, power, and area while ensuring successful physical design closure through collaboration with cross-functional teams.

Responsibilities

• Execute floorplanning, placement, clock tree synthesis (CTS), and routing activities for advanced technology nodes (16nm/7nm/5nm/4nm/3nm).
• Perform Static Timing Analysis (STA) and drive timing closure by identifying and resolving setup and hold violations.
• Develop and manage synthesis flows, timing constraints, and implementation methodologies.
• Conduct physical verification activities, including DRC and LVS debugging and closure using industry-standard tools.
• Implement and optimize Engineering Change Orders (ECOs), including clock push/pull adjustments, net-delay insertion, and shorts cleanup.
• Drive power-aware physical design implementation using low-power design techniques and methodologies.
• Collaborate with design, verification, and integration teams to ensure successful project execution and physical design closure.
• Work independently on synthesis, place-and-route (PnR), STA, physical design (PD), and physical verification (PV) closure for live projects.

Qualifications

• Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Minimum 3 years of experience in ASIC/SoC Physical Design implementation, exceptional entry-level candidates are encouraged to apply.
• Hands-on experience with Cadence Innovus is required.
• Strong understanding of digital physical design flow, including floorplanning, placement, CTS, routing, timing closure, and physical verification.
• Experience with Static Timing Analysis (STA), timing constraints, and synthesis methodologies.
• Familiarity with DRC/LVS verification and debugging using Calibre or equivalent tools.
• Proficiency in TCL scripting for automation and design flow enhancement.
• Knowledge of low-power design techniques and power-aware implementation methodologies.
• Experience working on advanced technology nodes is highly preferred.