UST Hiring! Full Time FPGA-RTL Design Engineer in Pulau Pinang - Ricebowl

We are seeking an experienced Senior FPGA/RTL Design Engineer with strong technical expertise in RTL design, VHDL, Verilog, Java, C, and hands-on experience with FPGA devices and tools. The ideal candidate will design, develop, verify, and optimize digital hardware architectures for high-performance embedded and hardware systems.

Key Responsibilities

FPGA / RTL Design

• Design, and implement RTL modules using VHDL and Verilog.
• Develop FPGA-based solutions using Quartus Prime design tools.
• Perform timing analysis, synthesis optimizations, and resource utilization improvements.
• Integrate, simulate, test, and debug FPGA designs in both pre-silicon and lab environments.

Verification & Validation

• Create and execute testbenches and verification plans for module- and system-level functionality.
• Use simulation tools (ModelSim, QuestaSim) to validate RTL behavior.
• Perform hardware bring-up, debugging, and validation using oscilloscopes, logic analyzers, and SignalTap.

Software / Firmware Integration

• Develop embedded software tools or scripts using C and Java.
• Collaborate with firmware and software teams to ensure seamless integration of FPGA-based components.

Documentation & Collaboration

• Prepare detailed design specifications, documentation, and test reports.
• Work closely with cross-functional teams.
• Mentor junior engineers in RTL design methodologies.

Required Qualifications

• Bachelor’s or Master’s Degree in Electrical Engineering or related field.
• 5+ years hands-on experience in FPGA design, RTL development, and digital logic.
• Strong proficiency in VHDL, Verilog, and RTL methodologies.
• Experience with FPGA platforms such as Cyclone, Arria, Stratix.
• Skilled in Quartus Prime, ModelSim/QuestaSim, and timing analysis tools.
• Programming experience in C and Java.
• Strong debugging and problem-solving skills.
• Excellent communication and teamwork abilities.