- Bayan Lepas Pulau Pinang Malaysia
UST Hiring! Full Time Associate III - VLSI in Pulau Pinang - Ricebowl
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Responsibilities
Role Description
Key Responsibilities RTL-to-GDSII Implementation: Own the entire physical design flow, from netlist to final GDSII delivery. Floorplanning & Partitioning: Define chip area, I/O placement, and layout constraints. Placement & Routing (PnR): Place standard cells and route wires using EDA tools (e.g., Cadence Innovus, Synopsys Fusion Compiler). Clock Tree Synthesis (CTS): Design the clock distribution network to meet timing and skew requirements. Physical Verification: Ensure layout adheres to design rules (DRC) and matches the schematic (LVS), along with antenna checks. Timing Closure & Optimization: Perform Static Timing Analysis (STA) and optimize for performance and power (PPA). Power & Reliability Analysis: Design power delivery networks (PDN) and check for IR drop/Electromigration (EM). ************* ************* +5 Required Skills and Qualifications Education: Bachelor s or Master s degree in Electrical/Electronics/Computer Engineering. Experience: 2-5+ years of experience in physical design at advanced nodes (e.g., 7nm, 5nm, 3nm). Tools: Expert proficiency in Synopsys (Design Compiler, IC Compiler II, Fusion Compiler) or Cadence (Genus, Innovus) tools. Scripting: Strong proficiency in TCL, Python, or Perl to automate design flows. Technical Skills: Deep understanding of VLSI design principles, low-power design techniques, and timing analysis.
Skills
vlsi design,rtl-to-gdsii,placement and routing,timing closure and optimization,
Key Responsibilities RTL-to-GDSII Implementation: Own the entire physical design flow, from netlist to final GDSII delivery. Floorplanning & Partitioning: Define chip area, I/O placement, and layout constraints. Placement & Routing (PnR): Place standard cells and route wires using EDA tools (e.g., Cadence Innovus, Synopsys Fusion Compiler). Clock Tree Synthesis (CTS): Design the clock distribution network to meet timing and skew requirements. Physical Verification: Ensure layout adheres to design rules (DRC) and matches the schematic (LVS), along with antenna checks. Timing Closure & Optimization: Perform Static Timing Analysis (STA) and optimize for performance and power (PPA). Power & Reliability Analysis: Design power delivery networks (PDN) and check for IR drop/Electromigration (EM). ************* ************* +5 Required Skills and Qualifications Education: Bachelor s or Master s degree in Electrical/Electronics/Computer Engineering. Experience: 2-5+ years of experience in physical design at advanced nodes (e.g., 7nm, 5nm, 3nm). Tools: Expert proficiency in Synopsys (Design Compiler, IC Compiler II, Fusion Compiler) or Cadence (Genus, Innovus) tools. Scripting: Strong proficiency in TCL, Python, or Perl to automate design flows. Technical Skills: Deep understanding of VLSI design principles, low-power design techniques, and timing analysis.
Skills
vlsi design,rtl-to-gdsii,placement and routing,timing closure and optimization,
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