全职 Physical Design Manager 工作, 薪水, Vhunt4u Perlis 公司招聘中 - Ricebowl

Company Description: Vhunt4u is a product development and solutions company focused on simplifying everyday life by integrating advanced technologies such as AI, Machine Learning, Robotics and Semiconductors. The solutions division delivers end-to-end AI, Telecom, and Semiconductor services to customers across the globe. Using a client-centric Global Engagement Model, Vhunt4u blends local senior on-site expertise with the scalability and cost advantages of offshore teams. This approach drives flexibility, quality, and value for clients. A strong commitment to long-term partnerships shapes how teams operate and empowers each associate to contribute meaningfully to customer success.

Role Description

• This is a techno managerial full-time role and you will be on payrolls of the group companies.
• You are required to be hands-on & ready to work on-site (customer location) based in Penang.
• This role is responsible for leading end-to-end physical design activities, including floor planning, place and route, clock tree synthesis, and closure of timing, power, and area for complex SoCs or ASICs.
• The manager will oversee power analysis, physical verification, and sign-off flows, ensuring designs meet performance, reliability, and manufacturability targets.
• Day-to-day responsibilities include guiding and mentoring the physical design team, defining methodologies and best practices, collaborating closely with RTL, verification, DFT, and architecture teams, and coordinating with foundries and EDA vendors as needed.
• The role also involves project planning, tracking milestones, reviewing design quality, and proactively resolving technical and schedule risks.
• VISA SPONSORED FOR QUALIFIED RESOURCES

Qualifications

• Bachelor's / Master's degree in engineering from EEE / E&C with 10+ years of expertise in ASIC PD
• 10+ years of experience in Top / Block level ASIC PnR implementation (RTL to GDSII).
• 10+ years of Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
• 10+ Years of Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
• Excellent communication and presentation skills, experience in collaborating with global teams.
• Experience in hierarchical designs and/or Low Power implementation is an advantage.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
• Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
• 3+ years of expertise in mentoring &, guiding junior engineers and be an effective team player.
• Expertise in Cadence Innovus, Tempus, Calibre