We are hiring Physical Design Engineers at all levels.
Key Responsibilities:
- Execute full-chip or block-level physical design for GPU/AI accelerator SoCs, from floorplanning to sign-off, optimizing for timing, power, and area (PPA) targets.
- Perform place & route, CTS, routing, optimization, timing closure, and physical sign-off (SI, IR/EM, DRC/LVS).
- Debug and resolve congestion, timing, and power integrity issues, including ECO support.
- Collaborate with RTL, architecture, and verification teams to improve physical implementation quality.
- Track execution progress and support activities to ensure on-time tape-out.
Job Requirements:
- Experience with physical design and signoff tools such as Synopsys Fusion Compiler / ICC2, PrimeTime, and Calibre.
- Good understanding of STA, power integrity (IR/EM), and signal integrity analysis.
- Scripting experience in Tcl, with knowledge of Python or Perl, is considered a plus for automation and process improvement.
- Proficient in working within a Unix/Linux environment.
Disclaimer: The salary range provided is for reference only. Final compensation will be determined based on the candidate's qualifications, experience, and job level.
Pay: RM4,500.00 - RM15,000.00 per month
Benefits:
- Additional leave
- Flexible schedule
- Health insurance
- Maternity leave
- Opportunities for promotion
- Professional development
- Work from home
Work Location: In person