Job Title: Senior DFT Engineer – Path Delay Fault
Experience: 10+ Years
Job Summary
We are seeking a highly experienced Senior DFT Engineer with strong expertise in Path Delay Fault (PDF) pattern generation, STA timing analysis, and silicon debug activities. The ideal candidate should be fully independent, self-driven, and capable of owning the complete DFT path delay fault flow from pattern generation to coverage improvement and silicon validation.
Key Responsibilities
- Develop and generate Path Delay Fault (PDF) ATPG patterns using Siemens Tessent tool chain.
- Analyze and interpret STA timing reports to identify critical and timing-marginal paths.
- Perform path selection, timing-aware ATPG, and pattern validation for high-speed designs.
- Debug and improve path delay fault coverage through detailed analysis and optimization techniques.
- Work closely with design, STA, physical design, and validation teams to resolve timing and testability issues.
- Perform silicon bring-up and silicon debug related to path delay fault patterns.
- Analyze tester failures, diagnose root causes, and drive corrective actions.
- Support DFT implementation, verification, and signoff activities for complex SoCs.
- Ensure high-quality deliverables with minimal supervision and independently drive project execution.
Required Skills & Qualifications
- Bachelor’s or master’s degree in Electronics/Electrical Engineering or related field.
- Minimum 10 years of hands-on DFT experience with strong focus on Path Delay Fault testing.
- Strong expertise in Siemens Tessent ATPG tool suite.
- Solid understanding of STA concepts, timing closure, and critical path analysis.
- Experience in silicon debug and tester failure analysis.
- Good understanding of scan, ATPG, compression, and fault coverage methodologies.
- Strong debugging, analytical, and problem-solving skills.
- Ability to work independently and lead technical activities with minimal guidance.
Preferred Skills
- Experience with advanced node SoC designs.
- Knowledge of scripting languages such as Tcl, Perl, or Python.
- Exposure to ATE environments and production test flows.