NSING TECHNOLOGIES INC. Hiring! Full Time Principal Design Engineer in - Ricebowl

Your Role:

You will play a key role in the front-end SoC development team, contributing to the architecture, RTL design, and integration of high-performance microcontroller SoCs. You will drive design quality, efficiency, and technical innovation while collaborating closely with cross-functional teams including verification, physical design, firmware, and system architects. You will also mentor junior engineers and help shape best design practices within the team.

• Collaborate with SoC architects to interpret specifications and convert them into implementable designs.
• Lead RTL microarchitecture definition and implementation for key SoC modules and subsystems.
• Develop design documentation including microarchitecture specifications and interface definitions.
• Design, code, and integrate high-quality RTL.
• Strong knowledge in SDC constraints.
• Perform design optimization for low power, area efficiency, and timing closure.
• Drive linting, CDC analysis, synthesis, and static timing checks to ensure sign-off quality RTL.
• Participate in RTL integration, resolving interface and system-level issues.
• Work closely with verification teams to define verification strategies and resolve design issues.
• Contribute to continuous improvement of design methodologies and reusable design components.
• Provide technical guidance and mentorship to junior RTL engineers.

Your Skills and Experiences:

Education:

• Bachelors or Master’s Degree in Electrical Engineering, Computer Engineering, or a related field.

Experience:

• 8+ years of hands-on experience in RTL design for ASIC or SoC development.

Technical skills you will need to have:

• Strong expertise in Verilog RTL design (VHDL exposure is a plus).
• Deep understanding of digital design fundamentals, SoC architecture, and microarchitecture.
• Familiar with AMBA bus protocols (AXI, AHB, APB).
• Experience in low-power design techniques (clock gating, power domains, retention).
• Strong understanding of synthesis constraints, timing analysis, and power optimization.
• Hands-on experience with EDA tools such as: Synopsys VCS, Verdi, Design Compiler

Preferred experience you have:

• Lead chip top level from design to tapeout.
• Hands-on synthesis, timing analysis.
• Exposure to FPGA prototyping and hardware validation.
• ARM based MCU.
• Experience integrating memory and peripheral interfaces like SRAM, SDRAM, QSPI, SPI, I2C, PWM, CAN, SDMMC.
• Experience in leading / guiding junior engineers.

Other Skills:

• Strong analytical and problem-solving skills, with a keen attention to detail.
• Ability to take ownership of design deliverables and drive technical decisions.
• Excellent communication and teamwork skills, with the ability to collaborate effectively in a cross-functional environment.
• Demonstrated leadership through mentoring, technical guidance, or project coordination.
• Self-driven, adaptable, and able to manage multiple priorities in a fast-paced environment.