Hiring: Design for Test (DFT) Engineer
Location: Penang, Malaysia
Employment Type: Permanent/Contract
Job Mode: Full Time - Onsite
Work Status: Only for people authorize to work in Malaysia (Local, PR or RPT only)
We are looking for an experienced Design for Test (DFT) Engineer to join our semiconductor design team. The ideal candidate will have hands-on experience in ASIC/SoC DFT implementation, ATPG, scan insertion, and test architecture development.
Key Responsibilities
- Develop and implement DFT architecture for ASIC/SoC designs.
- Perform scan insertion, scan compression, MBIST, LBIST, and JTAG implementation.
- Generate and debug ATPG patterns for various fault models.
- Verify DFT implementation through RTL and gate-level simulations.
- Work closely with Physical Design, RTL, Verification, and Product Engineering teams to ensure successful silicon bring-up and manufacturing test readiness.
- Support silicon debug, yield analysis, and test optimization.
Requirements
- Bachelor's or master's degree in electrical, Electronics, Computer Engineering, or a related field.
- 4–15 years of hands-on experience in ASIC/SoC DFT.
- Strong knowledge of Scan, ATPG, MBIST, LBIST, JTAG (IEEE 1149.1), and IJTAG (1687).
- Experience with one or more DFT tool suites:
- Synopsys: DFTMAX, TetraMAX, Design Compiler, Fusion Compiler
- Siemens/Mentor: Tessent, FastScan, TestKompress
- Cadence: Modus, Genus
- Good understanding of RTL design using Verilog/SystemVerilog.
- Scripting skills in Tcl, Python, or Perl are preferred.
- Strong debugging, analytical, and problem-solving skills.
Interested candidates are welcome to apply or send their updated resume to *************
#DFT #ASIC #SoC #Semiconductor #VLSI #ATPG #MBIST #LBIST #JTAG #ScanInsertion #PhysicalDesign #Hiring #Jobs #Engineering #Malaysia