Design Automation Engineer – Layout Extraction
Location: Penang, Malaysia (Onsite)
Experience: 4+ years (Intermediate to Senior)
Start Date: Urgent hiring – fast interview process
About the Role
In this role, you will focus on layout extraction and physical verification for advanced SoC designs, working with cutting-edge tools and large-scale chip projects.
Key Responsibilities
- Develop and maintain automated signoff flows for layout extraction
- Perform Parasitic Extraction (PEX) using industry tools
- Work with tools such as Siemens Calibre or Synopsys StarRC
- Troubleshoot LVS (Layout vs. Schematic) issues
- Optimize tool runtime for large-scale SoC designs
- Automate workflows using scripting (Python, Perl, Tcl)
Requirements (Must-Have)
- 4+ years of experience in physical design / design automation
- Strong hands-on experience with:
- Siemens Calibre or Synopsys StarRC
- Solid understanding of:
- Layout extraction (PEX)
- LVS verification
- Experience with scripting (Python / Perl / Tcl)
- Familiar with semiconductor design flow and PDK validation
Nice to Have
- Experience with large-scale SoC projects
- Optimization experience for runtime/performance
- Exposure to advanced nodes (e.g., 7nm, 5nm)