全职 Senior Analog Layout Engineer 工作, 薪水, Vchip Penang Pulau Pinang 公司招聘中 - Ricebowl

About the Job

V-Chip is an IC design service company and a subsidiary of Sai Microelectronic, a China-listed company recognized as the world's largest MEMS foundry. We support clients across the full chip development lifecycle — from architecture planning and IP selection to design verification, custom analog design, and physical design. In September 2025, V-Chip established an IC design facility in Penang, Malaysia's premier semiconductor hub, as part of its global expansion, focused on building local engineering capability while collaborating with universities and research institutions.

We're looking for a Senior Analog Layout Design Engineer to own high-value analog and mixed-signal layout blocks end-to-end, from floorplanning through tape-out, and to help mentor and grow our layout team in Penang.

The Role

As a Senior Analog Layout Design Engineer, you will collaborate closely with circuit designers to translate schematics into robust, silicon-ready layouts. You'll take full ownership of complex analog/mixed-signal blocks — from floorplanning and power/signal routing through DRC/LVS sign-off — while guiding design decisions on matching, shielding, and isolation for sensitive analog circuits. You'll also mentor junior layout engineers and help shape our layout methodology and flow standards as the Penang team scales.

Key Responsibilities

• Own transistor-level layout of complex analog, digital, and mixed-signal blocks from floorplan through tape-out
• Lead floorplanning, power grid planning, and signal flow planning in close collaboration with analog designers
• Conduct and sign off on physical/electrical verification: DRC, LVS, ERC, EM/IR, latch-up, and ESD checks
• Apply advanced matching, shielding, and isolation techniques for precision, low-noise, and high-performance analog circuits
• Review design specifications and support design reviews and sign-off decisions
• Mentor junior layout engineers and contribute to layout methodology, best practices, and flow improvement
• Track and report progress against block-level schedules and milestones

Qualifications

• 5+ years of hands-on experience in analog or mixed-signal IC layout design
• Strong understanding of CMOS circuit theory and analog design fundamentals for precision, low-noise, and high-performance applications
• Hands-on expertise with Cadence Virtuoso and Calibre (DRC/LVS/ERC), and familiarity with foundry PDKs
• Solid experience with EM/IR, latch-up, and ESD verification flows
• Proven track record applying matching, shielding, and isolation techniques in production designs
• Experience mentoring junior engineers and contributing to layout methodology/flow improvement
• Bachelor's or Master's degree in Electrical/Electronic Engineering or related field
• Strong communication skills to work effectively in a multicultural, cross-functional environment

Location & Work Authorization

• This is a full-time, on-site role based in Penang, Malaysia. Candidates must be currently based in Malaysia or eligible to work in Malaysia without sponsorship.