全职 ASIC Design Verification Engineer 工作, 薪水 up to SGD 8,000, TETRAMEM SINGAPORE PTE. LTD. Islandwide (Singapore) 公司招聘中 - Ricebowl

In this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will completely disrupt the AI IoT landscape. It is based on our unique computing memory device with multi-bit-level capacity per cell, which is non-volatile with excellent retention and endurance. We offer a very competitive compensation, commensurate with experience, and a full benefits package including insurance, paid time off, and more.

Multiple job openings including Engineer, Senior Engineer, etc. position levels and salary are determined by background and experience.

Responsibilities:

• Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
• Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
• Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioural modules for both block levels and system levels.
• Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out
• Work with design engineers to debug and identify root causes of simulation failure
• Support test engineers for post-silicon validation
• Mentor and coach junior engineers. Drive verification efficiency

Requirements:

• MS with 4+ years of relevant experience or PhD in Electrical Engineering, Computer Engineering, Computer Science or related degree
• In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology
• Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and test cases development for function/performance verification
• Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding
• Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core
• Experience in verifying designs at both RTL level and post-P&R gate level
• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
• Experience in verifying mix-signal design and interface of digital and analog
• Experience of design verification for high-speed IO such as PCIE and DDR