全职 Sr. Physical Design Engineer 工作, 薪水, Quest Global Pulau Pinang 公司招聘中 - Ricebowl

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

5-10 years’ experience with bachelor’s degree in Electronics Engineering or equivalent

• Experience in Physical Design with PNR flow from RTL to GDS flow,
• Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.
• Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
• Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
• Experience in modifying STA constraints to check timing closure feasibility
• Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm

Work Experience

• 5-10 years’ experience with bachelor’s degree in Electronics Engineering or equivalent
• Experience in Physical Design with PNR flow from RTL to GDS flow,
• Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.
• Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
• Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
• Experience in modifying STA constraints to check timing closure feasibility
• Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm

Benefits

Competitive Benefit