全职 Design Verification Engineer (Memory) - Junior-Senior 工作, 薪水, SkyeChip Pulau Pinang 公司招聘中 - Ricebowl

Location (on-site): Malaysia (Penang)

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Role Summary

We are seeking a skilled Design Verification Engineer to join our team and contribute to the verification of complex digital IP designs. The ideal candidate will develop and execute comprehensive verification environments and methodologies to ensure design correctness and functional coverage closure. This role offers opportunity to work on cutting-edge silicon designs, and excellent learning path in collaborative engineering culture with cross-functional exposure. Join us for career growth and development opportunities. 

Key Responsibilities

• Develop and maintain UVM-based verification environments, including testbenches, sequences, scoreboards, and functional coverage models

• Write directed and constrained-random test cases to verify RTL designs against architectural and microarchitectural specifications

• Develop and execute verification plans with clear coverage goals and milestones

• Debug test failures through log analysis, waveform inspection, and root-cause identification • Drive functional coverage to closure and analyze coverage gaps

• Collaborate with RTL designers, architects, and firmware engineers to resolve design issues

• Participate in specification and design reviews to provide verification perspective

• Support regression infrastructure and triage regression failures

• Contribute to continuous improvement of verification methodologies and reusable components 

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field

• 3+ years of experience in ASIC/IP design verification

• Strong proficiency in SystemVerilog and UVM methodology

• Experience with constrained-random verification, functional coverage, and assertion-based verification (SVA)

• Solid understanding of digital logic design, computer architecture fundamentals. Advantage if there's good understanding in memory device such as HBM, LPDDR, DDR.

• Hands-on experience with industry simulators (VCS, Questa, Xcelium) Page 1 of 2

• Proficiency with debug tools (Verdi, DVE, or equivalent)

• Strong analytical and problem-solving skills

• Effective communication and collaboration skills

• Added advantages, preferred qualifications

o Experience with formal verification (FPV, connectivity checks)

o Familiarity with memory subsystems, high-speed interfaces (DDR/LPDDR, HBM), or SerDes PHY verification

o Experience with coverage-driven verification closure and URG report analysis

o Familiarity with DFT concepts (scan, BIST, JTAG)

o Experience with firmware-driven verification or co-simulation environments

o Knowledge of version control systems (Git, Perforce) and CI/CD pipelines for verification

o Scripting: Proficiency in scripting languages (Python, Perl, Tcl, or shell scripting) for test automation, regression management, log parsing, coverage analysis, and workflow optimization

o Knowledge in Gate-Level Simulation (GLS) is a plus: Experience with post-synthesis and post layout gate-level simulations, including SDF back-annotation, timing-aware verification, and debugging X-propagation and timing-related failures