全职 Senior RTL Design Engineer (Semiconductor) 工作, 薪水 up to SGD 12,000, INTELLIPRO SINGAPORE PTE. LTD. 公司招聘中 - Ricebowl

Responsibilities

• Mixed-signal subsystem design from design implementation to final delivery for chip-level integration.
• Perform micro-architectural studies to determine optimal hardware implementations of IP digital blocks to meet product requirements.
• Ensure all required documentations are prepared according to the quality standards.
• RTL logic design of modules using Verilog HDL. Designs may include power and clock management units, IIC, I2C, SoundWire digital interfaces, digital filters, etc.
• Prepare and hold design and verification reviews with technical staff throughout project lifecycle. • Perform logic synthesis, timing and power analysis to optimise designs.
• Pre-silicon verification utilizing various methodologies such as constrained random verification with block/subsystem/chip level UVM test benches, spice co-simulation of mixed signal blocks and FPGA emulation.
• Support Validation/bring-up of designs on silicon, providing support to cross-functional teams.

Requirements:

• Bachelor or Master Degree in Electrical and Electronic Engineering with minimum 7+ years of professional experience in digital CMOS IC design.
• Experience using high-level modelling language/tool for designing and evaluating subsystems and algorithms.
• Strong understanding of digital design, preferably in IIC, I2S, SoundWire interface design.
Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools, Verilog RTL design.

License No.22C1076 | EA Reg. No.: R25142215