jobs in UST Malaysia

全职 FPGA Engineer 工作, 薪水, UST Malaysia Pulau Pinang 公司招聘中 - Ricebowl

分享
保存

工作地点

  • Bayan Lepas Pulau Pinang Malaysia

职位描述

岗位职责

Technical Competencies

  • Proficiency with HDL design such as Verilog, System Verilog, and VHDL.
  • Experience working with standard FPGA development tools for various vendors: Xilinx Vivado, Vitis / Quartus / Diamond, Radiant, etc.
  • Experience working with simulation tools such as ModelSim and / or QuestaSim
  • Familiar with various high-speed interfaces such as PCIe, Ethernet (L1 – L4), USB, DDR, LVDS, etc.
  • Familiar with various low speed interfaces such as SPI, I2C, UART, etc.


Preferred experiences

  • Experience FPGA developer.
  • Familiar with DSP design, simulation, and implementation.
  • Knowledge of RF chipset and product development.
  • Firmware/driver development knowledge is an added advantage.


Job Requirements

  • Bachelor degree in Electrical/Electronic engineering or equivalent.
  • Minimum 3-5 years of direct working experiences in FPGA HDL/IP design experience.
  • Fluent in both written and spoken English, ability to work in an international team.
  • Good team work attitude, collaboration and communication skills.
  • Willing to work in Bayan Lepas, Penang Malaysia.


重要安全守则

申请工作时,切勿提供您的银行或信用卡详细资料。不要转账或完成无关的在线调查问卷。如果您发现可疑内容,请举报此招聘广告。

了解更多