全职 SoC DFX Timing Engineer 工作, 薪水, Wipro Pulau Pinang 公司招聘中 - Ricebowl

THE ROLE:

This engineer will mainly focus on full-chip test mode timing signoff and SDC quality check tasks. Moreover, he/she is expected to support cross-die STA and STA automation flow enhancement tasks.

THE PERSON:

Good team worker with solid Verilog RTL design knowledge/experience. Knowledge reservation on Synthesis/Scan/BIST/Multiple_Power timing signoff will be a strong plus.

KEY RESPONSIBILITIES:

· Cutting-edge test strategies study and implementation.

· DFT sdc development and maintenance.

· Support special timing check and multi-voltage timing check.

· Timing sign-off automation flow enhancement.

· Co-work with Front End design team for synthesis optimization and sdc quality check.

· Co-work with Physical design team for full chip smooth timing signoff.

PREFERRED EXPERIENCE:

· Solid background on process, device or ASIC design.

· Strong technical background in Verilog coding.

· Experience in Design Compiler, Fusion Compiler and Primetime EDA tools will be a plus.

· Good knowledge on DFT Scan/BIST will be a strong plus.

· Good knowledge on CTS and ICC physical design flow will be a strong plus.

· Proven knowledge and expertise on two or more fields of SCAN, MBIST, RTL design, STA and DV.

· Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.

· Good communication skills (both English and Mandarin) and self-driven, willing to learn/share.