全职 CPU Design Engineer - Singapore 工作, 薪水, Espressif Systems 公司招聘中 - Ricebowl

Job Responsibilities

1. Design, verify, and optimize CPU microarchitecture to meet instruction set architecture (ISA) functional and performance requirements.
2. Design processor datapaths, control logic, and memory hierarchy.
3. Research and apply advanced techniques—such as superscalar execution, multithreading, branch prediction, out-of-order execution, and multi-level caches—to improve processor performance and efficiency.
4. Work closely with other hardware engineers, software engineers, and verification engineers to ensure thorough validation of CPU functionality and performance.
5. Write and maintain CPU design documentation, including specifications, functional descriptions, and microarchitecture manuals, to support hardware and software development teams.
6. Design multi-core and heterogeneous processor architectures.

Qualifications

1. Bachelor’s degree or above in Computer Engineering, Electrical Engineering, Microelectronics, or related fields.
2. Preferably 5 years of CPU design experience, with solid knowledge of processor architecture, microarchitecture, datapath design, control logic, and memory hierarchy.
3. Familiarity with the C910 instruction set and related processor architectures; prior experience designing processors based on this architecture is a plus.
4. Proficiency in hardware description languages such as Verilog or VHDL, with strong logical design and engineering implementation skills.
5. Solid understanding of computer architecture and operating system principles, and knowledge of processor performance and efficiency optimization techniques.
6. Strong teamwork skills, good communication and organizational abilities, and good English reading and writing skills, with the ability to read and write technical documentation and reports.

Preferred Qualifications

1. Experience with performance modeling, simulation, and verification; familiarity with computer architecture and performance analysis tools.
2. Experience in RISC-V processor architecture design.
3. Experience in CPU microcode design and optimization.
4. Experience in CPU power management and power optimization.
5. Experience in implementing CPU security and cryptography technologies.